OVERVIEW

The CHI-based mesh interconnect is a scalable, high-performance communication fabric designed to connect a large number of nodes in modern SoC architectures. Built on a distributed mesh topology, it enables efficient packet-based transaction routing while maintaining low and predictable latency.

The interconnect supports AMBA CHI-compliant interfaces, enabling communication between request nodes (RN), home nodes (HN), and slave nodes (SN) using independent Request, Response, and Data channels. The design focuses on high-throughput transaction transport without implementing cache coherency, making it suitable for non coherent or loosely coupled systems.

To maximize performance, the interconnect supports parallel processing across independent CHI channels and multiple outstanding transactions. Configurable transaction ordering and QoS mechanisms allow tuning for latency, fairness, and throughput. Multiple routing algorithms are supported to optimize traffic distribution, reduce congestion, and improve overall network efficiency. The mesh architecture also enables scalable expansion to large node counts without fundamental redesign

The interconnect provides flexibility for system integration through configurable address mapping and internal data width, allowing trade offs between bandwidth, power, and area.

Robust system management features include advanced interrupt handling, per-channel watchdog timers for detecting stalled transactions, and independent software-controlled reset for each node interface to enable localized fault isolation.

Designed for complex clocking environments, each node interface operates in an independent clock domain. Register slicing supports clean clock-domain crossings and timing closure, while internal clock gating reduces dynamic power consumption during low activity periods. With deterministic per-hop latency, the mesh interconnect delivers predictable performance for large-scale SoC designs.

Delivered as a synthesizable RTL IP optimized for power, performance, and area (PPA), the CHI-based mesh interconnect provides a scalable and production-ready solution for high-bandwidth, multi-node SoC platforms.